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ERIK PILMANIS

Putnam Valley, NY 10579

919-870-0608

(word version)

 

SUMMARY   Over 21 years experience in digital hardware engineering including:

·        Experience in High Speed hardware design.
·        FPGA, ASIC, and PCB design including: Telecom, Network,Video, RF, Optical network, Processor, and Network applications.

·        Expertise in VHDL and Verilog HDL: Synthesis, Modeling, andfunctional/gate/system/post layout level verification.

 

EXPERIENCE

Adapticom Incorporated                                                    Raleigh, NC

 

11/2005 – Present :  Consultant, FPGA/VHDL

·        Consultant on FPGA & VHDL tools & projects.


                       

Northrop Grumman Corporation                                                     Norwalk, CT

 

9/2003 – 11/2005 : FPGA/VHDL Designer.

·        HDL verification for NGC’s  Direct Digital Synthesis ASIC. Test bench designed in VHDL to verify DDS ASIC models.

·        Hardware verification for NGC developed DDS ASIC. Designed a high speed test system used to operate the DDS ASIC under varying in-circuit conditions. Design included: PCB design, FPGA design and verification in VHDL, host interface, hardware and software specification, and software co-design.

·        Designed/Simulated Direct Digital Synthesis interface FPGA for Multi Mode radar platform implemented in a Xilinx Spartan III FPGA. Design connected a proprietary bus standard to a custom DDS ASIC, and generated timing/synchronization signals.  

·        Designed/Simulated L and X Band Synthesis interface FPGA for Multi Mode Radar system implemented in a Xilinx Spartan III FPGA.  Circuit operation was achieved with no external synchronous clock and utilized available asynchronous signals for timing.

·        Designed/Simulated Channel Correction FPGA design implemented in a Xilinx Virtex II Pro P70 FPGA including a 128-tap/32 bit precision FIR filter running at 270 MHz (540MHz input data rate). FIR filter speed was achieved by generating RLOC routing directives within the VHDL code. Automatic 4 channel clock to data phase correction circuit designed to align multiple frequency data streams to selectable input clocks.  

·        Digital IQ Demodulator Bus Interface FPGA implemented in a XILINX Virtex II Pro P70 used to connect host Tundra PCI/VME bridge to FIR filter and Serial FPDP FPGA’s including 2 DIQ ASIC’s. Design supports VME 32 and 64 bit bus standards.      

·        Designed/Simulated Serial FPDP SERDES/MGT design implemented in a XILINX Virtex II P70 FPGA. 4 Systran Serial FPDP cores were used in conjunction with data steam framing, header insertion, and multiple AGC mode designs(system speed 250Mhz).

Northrop Grumman Corporation  Continued

·        All above designs written and simulated in VHDL utilizing the following tools: Modelsim SE 5.6, Synplify Pro 7.3.4, Xilinx ISE 6.2.2, and HDL

           Designer Pro.    

·        Architected and designed high speed Digital IQ card test system utilizing a 2 component PCB module. Features include: High speed LVDS vector generation and interface, RS232 and Ethernet host interface, VME bus

exerciser and analyzer. Test vector generation and capture accomplished through the use of a Xilinx  Virtex II Pro P2 FPGA with MicroBlaze soft processor, host interface, and host test application.  

·        Architected and designed Digital Interface card test system utilizing a 3 component PCB module. Features include: RS422/RS485/LVDS interfaces to the UUT, RS232/Ethernet/USB host interface, Xilinx Spartan III FPGA for vector generation and capture.

FPGA used to generate and capture test vectors from MATLAB generated files. Test vector execution and control achieved through a RS232 host interface.

Documentation and specification, hardware/software interface, test procedure and features,  FPGA design and verification in VHDL, synthesis, and  FPGA place and route.

 

Circadiant Systems                                                                       Allentown, PA

 

4/2002 – 9/2003 : FPGA/VHDL/PCB Designer.      

Pivotech Systems                                                                        Piscataway, NJ

 

11/2001 – 4/2002 : PCB/FPGA/CPLD/Verilog Designer

FPGA, CPLD, DSP and Analog interface (AFE) circuitry.

 

Actel Corporation                                                                      Mt. Arlington, NJ

 

10/2000 – 11/2001 : FPGA/VHDL/Verilog Designer

 

 

IBM Microelectronics Division                                                       Hopewell, NY

 

5/2000 – 10/2000 : FPGA/VHDL Designer

 

Tellium Inc.                                                                                     Oceanport, NJ

 

11/1999 – 5/2000 : FPGA/VHDL Designer

 

 

Lucent Technologies                                                                     Whippany, NJ

 

2/1999 – 11/1999 : ASIC/FPGA/VHDL Designer

 

 

IBM Research Division                                                                   Yorktown, NY

 

8/1996 – 2/1999 : ASIC/FPGA/VHDL Designer

 

           and ASIC tool suite.

 

 

Desk Net Systems                                                                             Armonk, NY

 

1/1996 – 8/1999 : FPGA/PCB Designer

 

and Lattice CPLD’s.

 

 

 

 

IBM Research Division                                                                   Yorktown, NY

 

3/1995 – 8/1996 : FPGA/PCB Designer

 

 

 

 

 

IBM Research Division                                                                   Yorktown, NY

 

3/1992 – 3/1995 : FPGA/PCB Designer

 

 

 

 

 

 

 

Video Technologies Corporation                                              WestMilford, NJ

 

5/1989 – 3/1992 : Design Engineer

 

   

 

 

Kearfott Guidance and Navigation                                                     Wayne, NJ

 

2/1984 – 5/1989 : Design Engineer

 

 

 

EDUCATION

 

BS – Electronics Engineering : Fairleigh Dickinson University, Teaneck, Honors

 

MS – Computer Science :  Polytechnic University                        Hawthorne, NY