Rev. B, 05/17/00
Instruction traces represent one of the biggest collection challenges in the world of realtime tracing. Enough data must be collected from the processor bus to allow post processing software to recreate the instruction stream. Historically, this has been accomplished by collecting all "memory code read" or "fetch" bus cycles and recreating the prefetch queue of the processor within the trace hardware. Pins on the processor would indicate when instructions were executed. As instructions were retired, their opcodes would be removed from the prefetch queue and placed in the trace data stream.
As internal processor clock speeds began exceeding processor external bus speeds, the use of external signals to indicate instruction execution became impractical and was soon discontinued. As a result, collecting instruction traces from today's processors would require much more than simple prefetch emulation. In fact the trace tool must emulate many aspects of the processors execution unit.