FPGA Design

 Experience Summary

Rev. "B" 11/21/04
C. McCord

I have been developing programmable logic devices since the late 1980's.  The number I have designed is too large to know for certain, but I would say somewhere between 300 and 600 designs.   I will skip any discussion of the smaller PALs and focus on the more complex FPGAs. 

I began designing with FPGAs in 1989, when I utilized Actel OTP devices in designs for the IBM PC Radio.  I continued to use the Actel devices (because of their speed) throughout the early '90s.  Many of the devices were quite complex, particularly for their time.  In one design I emulated the complete pre-fetch queue for the Intel 80386.

 In the mid '90s I conducted and evaluation for IBM of Actel, Altera, and Xilinx FPGAs.  As a result, our group (IBM Server Performance) ultimately switched to using Xilinx parts.   All of these designs were quite complex.  In the late '90s I conducted a performance analysis of FPGA designs completed in Verilog, VHDL, and schematic capture.  We used the largest most complex Xilinx parts available as part of a piece of custom test equipment known as the "Real-time Trace Tool"  The required functions required so much logic that four of the largest Xilinx parts were required for the task.  The tool monitored, in real-time, all the bus activity of all the Intel processors.  This meant that the FPGAs were required to perform complex logic tasks at the speed of the processor "front side bus".

 In 2002 and 2003 I conducted an analysis of security vulnerabilities in re-configurable FPGAs (Xilinx, Altera, & Actel Flash).   Subsequent to that, in 2004 I developed Verilog based designs for Actel ProASIC, Altera Max 3000, and Xilinx Spartan II, using Verilog, Viewlogic, Modelsim, and associated development tools.  The complexity of these designs was not as great as earlier designs as the goal of the project was to fill each device to a equal, known capacity with similar structures (timers, counters, etc) and then experiment with the development tools of all the vendors to determine which tools and devices best facilitated the design concept of "Red/Black Data Separation", in which encrypted data must be partitioned separately from non-encrypted data.
 

Although my experience is predominantly with Verilog, I used VHDL as recently as last year (our initial development tools supplied by Actel only supported VHDL, so I used that tool set until we could get it replaced with the Verilog version.

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